Silicon IPs Library: Microcontroller

Catalog of 8-bit and 16-bit Microcontroller from:

 
Core
Optimization
process
DOWNLOAD
Seduction
Charm
Design-in
Integration
 
Flip8051
Presentation Sheet
(speed/ 80C51)		        

Breeze
(x 1)
100% cycle compatible
0.13 µm
0.18 µm
0.25 µm
NCSIM
Modelsim
SMASH
On request
On request
Wind
(x 2.8)
Lowest Cost
0.13 µm
0.18 µm
0.25 µm
NCSIM
Modelsim
SMASH
On request
On request
Thunder
(x 5.7)
Best ratio
Performance / Complexity
0.13 µm
0.18 µm
0.25 µm
NCSIM
Modelsim
SMASH
On request
On request
Cyclone
(x 8.8)
Highest processing power
0.13 µm
0.18 µm
0.25 µm
NCSIM
Modelsim
SMASH
On request
On request
WHIRL(8/16)
-Thunder
(x 6.6 / x 8.2)
Best ratio
Performance / Complexity
with unique DSP capabilities!
0.13 µm
0.18 µm
0.25 µm
Presentation Sheet
NCSIM
Modelsim
SMASH
On request
On request
WHIRL(8/16)
-Cyclone
(x 9.5 / x 11.1)
Highest processing power
with unique DSP capabilities!
0.13 µm
0.18 µm
0.25 µm
NCSIM
Modelsim
SMASH
On request
On request
Microcontroller Configuration
Flip80515
set of peripherals compliant with standard 80515 from Infineon
         
Flip83152
set of peripherals compliant with standard 83C152 from Intel
         
Flip80251
Presentation Sheet
(speed/ 80C251 & 80C51)
Typhoon
(x 2 / 80C251)
(x 30 / 80C51)

Best ratio
Performance / Complexity
Up to 30 times faster than a 80C51

0.13 µm
0.18 µm
0.25 µm
NCSIM
Modelsim
SMASH
On request
On request

Hurricane
(x3 / 80C251)
(x45 / 80C51)

Highest processing power.
Up to 45 times faster than a 80C51

0.13 µm
0.18 µm
0.25 µm
Datasheet
ISS of µVision
NCSIM
Modelsim
SMASH
On request
On request

* Cell library stem : Sesame, standard cell library

Specific Controllers and Interfaces : HDLC, I2C, SPI

High Data Link Controller with parameterized FIFO Controller
I2C-Bus Master/Slave Interface IP core, compatible with Philips I2C Protocol
SPI IP core: Synchronous Serial Peripheral Interface

 

:: SEDUCTION Front-end:

  • * Preliminary Promotion Sheet including data relative to the firm or hard version (area, power consumption)
  • * Datasheet
  • * ISS
  • * Application note explaining how to configure the ISS for a Flip8051/251 target

 

:: CHARM Front-end:

  • * Simulation model including checkers for memory bus and SFR bus
  • * Associated Virtual testbench enabling to run benchmark (dhrystone 1.1)
  • * Dhrystone program
  • * Application note explaining how to interpret the result of the simulation
  • * ViC specification

 

:: DESIGN-IN Front-end:

  • * Timing wrapper enabling back annotation of the simulation model with SDF file
  • * Virtual testbench + test vectors for code coverage
  • * User manual
  • * Power and timing analysis view, for one SESAME stem and one optimization, in .LIB format
  • * SUCCESS (optional)

 

:: INTEGRATION Front-end:

  • * Industrial test specification
  • * Test patterns for industrial test in WGL format
  • * Summary of the faults detected with the fault coverage rate
  • * Footprint of the component in VC LEF format